26”
TFT TV is a progressive TV control system with built-in de-interlacer and
scaler. It uses a 1280*768 panel with 16:9 aspect ratio.
The TV is capable of
operation in PAL, SECAM, NTSC (playback) colour standards and multiple
transmission standards as B/G, D/K, I/I’, and L/L´ including German and NICAM
stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8Ω speakers.
The chassis is equipped with many inputs and outputs allowing it to be used as
a center of a media system.
The UV1316
tuner belongs to the UV 1300 family of tuners, which are designed to meet a
wide range of applications. It is a combined VHF, UHF tuner suitable for CCIR
systems B/G, H, L, L’, I and I’. The low IF output impedance has been designed
for direct drive of a wide variety of SAW filters with sufficient suppression
of triple transient.
The TDA9886
is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF
signal PLL Both devices can be used for TV, VTR, PC and set-top box
applications.
VIF
amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop
(FPLL) detector, VCO and divider, Digital acquisition help and AFC, Video
demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC detector,
Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help,
Audio amplifier and mute time constant, I²C-bus transceivers and MAD (module
address), Internal voltage stabilizer.
The MSP34x1G
family of single-chip Multistandard Sound Processors covers the sound
processing of all analog TV-Standards worldwide, as well as the NICAM digital
sound standards. The full TV sound processing, starting with analog sound IF
signal-in, down to processed analog AF-out, is performed on a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments.
In
case of three or more external sources are used, the video switch IC TEA6415 is
used. The main function of this device is to switch 8 video-input sources on
the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same input connected to several outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible to have the same input connected to several outputs.
The TPA3002D2
is a 9-W (per channel) efficient, Class-D audio amplifier for driving
bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakersas low as
8 &. The high efficiency of the TPA3002D2 eliminates the need for external
heatsinks when playing music.
The
DC voltages required at various parts of the chassis and inverters are provided
by an main power supply unit and power interface board. The main power supply
unit is designed for 24V and 12V DC supply. Power interface board generates
+12V for audio amplifier, 5V and 3.3V stand by voltage and 8V, 12V, 5V and 3V3
supplies for other different parts of the chassis.
An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation circuit in secondary side. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations.
An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation circuit in secondary side. During the switch on period of the transistor, energy is stored in the transformer. During the switch off period energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations.
The
microprocessor is embedded inside PW181 chip which also handles scaling, frame
rate conversion and OSD generation. The on-chip 16-bit microprocessor is a
Turbo x86-compatible processor core with on-chip peripherals (timers, interrupt
controller, 2-wire serial master/slave interface, UART, I/O ports, and more).
Special peripherals such as Infrared (IR) pulse decoders and a digital pulse
width modulator (PWM) are also included. There are two independent 2-wire
serial master/slave interface modules that can be multiplexed to control up to
five 2-wire serial ports. The slave 2-wire interface is designed for HDCP use
only (and requires the use of HDCP Image Processors). On-chip RAM of up to 64
Kbytes is available. A complete microprocessor system can be implemented simply
by adding external ROM. The on-chip processor can be disabled to allow external
processor control of all internal functions.
The
Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically
Erasable PROM. It has been developed for advanced, low power applications such
as personal communications or data acquisition. The 24C32A also has a
page-write capability of up to 32 bytes of data. The 24C32A is capable of both
random and sequential reads up to the 32K boundary. Functional address lines
allow up to eight 24C32A devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology and broad voltage range make this device ideal
for low-power/low-voltage, non-volatile code and data applications.
The TDA1308
is an integrated class AB stereo headphone driver contained in a DIP8 plastic
package.
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.
IC
DESCRIPTIONS
TDA9886
TEA6415C
24C32
SAA5264
LM317T
ST24LC21
TLC7733
74LVC257A
74LVC14A
LM1117
IRF7314
IRF7316
MC34063A
LM2576
DS90C385
MSP3411G
TPA3002D
TDA1308
PI5V330
AD9883A
SAA7118E
TPS72501
TSOP1136
PCF8591
PW1231
PW181
SIL151B
SDRAM 4M x 16 (MT48LC4M16A2TG-75)
FLASH
The TDA9885
is an alignment-free single standard (without positive modulation) vision and
sound IF signal PLL
TEA6415C
24C32
SAA5264
LM317T
ST24LC21
TLC7733
74LVC257A
74LVC14A
LM1117
IRF7314
IRF7316
MC34063A
LM2576
DS90C385
MSP3411G
TPA3002D
TDA1308
PI5V330
AD9883A
SAA7118E
TPS72501
TSOP1136
PCF8591
PW1231
PW181
SIL151B
SDRAM 4M x 16 (MT48LC4M16A2TG-75)
FLASH
•
5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC bits via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD)
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC bits via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD)
TEA6415C
The
main function of the IC is to switch 8 video input sources on 6 outputs. Each
output can be switched on only one of each input. On each input an alignment of
the lowest level of the signal is made (bottom of synch. top for CVBS or black
level for RGB signals). Each nominal gain between any input and output is
6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing,
with an external resistor bridge, 5 VDC on the input. Each input can be used as
a normal input or as a MAC or Chroma input (with external resistor bridge). All
the switching possibilities are changed through the BUS. Driving 75Ω load needs
an external transistor. It is possible to have the same input connected to
several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration.
several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configuration.
24C32A
The
Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically
Erasable PROM. It has been developed for advanced, low power applications such
as personal communications or data acquisition. The 24C32A also has a
page-write capability of up to 32 bytes of data. The 24C32A is capable of both
random and sequential reads up to the 32K boundary. Functional address lines
allow up to eight 24C32A devices on the same bus, for up to 256K bits address
space. Advanced CMOS technology and broad voltage range make this device ideal
for low-power/low-voltage, non-volatile code and data applications. The 24C32A
is available in the standard 8-pin plastic DIP and both 150 mil and 200 mil
SOIC packaging.
•
Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Standby current 1 mA typical at 5.0V
• 2-wire serial interface bus, I2CTM compatible
• 100 kHz and 400 kHz compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
- Commercial (C): 0°C to 70°C
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
- Maximum write current 3 mA at 5.5V
- Standby current 1 mA typical at 5.0V
• 2-wire serial interface bus, I2CTM compatible
• 100 kHz and 400 kHz compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
- Commercial (C): 0°C to 70°C
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
The
24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled by a master device which
generates the Serial Clock (SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C32A works as slave. Both master and
slave can operate as transmitter or receiver but the master device determines
which mode is activated
Following features apply to both SAA5264 and SAA5265:
• Complete 625 line teletext decoder in one chip reduces printed circuit board area and cost
• Automatic detection of transmitted fastext links or service information (packet 8/30)
• On-Screen Display (OSD) for user interface menus using teletext and dedicated menu icons
• Video Programming System (VPS) decoding
• Wide Screen Signalling (WSS) decoding
• Pan-European, Cyrillic, Greek/Turkish and French/Arabic character sets in each chip
• High-level command interface via I2C-bus gives easy control with a low software overhead
• High-level command interface is backward compatible to Stand-Alone Fastext And Remote Interface (SAFARI)
• 625 and 525 line display
• RGB interface to standard colour decoder ICs, current source
• Versatile 8-bit open-drain Input/Output (I/O) expander, 5 V tolerant
• Single 12 MHz crystal oscillator
• 3.3 V supply voltage.
• Complete 625 line teletext decoder in one chip reduces printed circuit board area and cost
• Automatic detection of transmitted fastext links or service information (packet 8/30)
• On-Screen Display (OSD) for user interface menus using teletext and dedicated menu icons
• Video Programming System (VPS) decoding
• Wide Screen Signalling (WSS) decoding
• Pan-European, Cyrillic, Greek/Turkish and French/Arabic character sets in each chip
• High-level command interface via I2C-bus gives easy control with a low software overhead
• High-level command interface is backward compatible to Stand-Alone Fastext And Remote Interface (SAFARI)
• 625 and 525 line display
• RGB interface to standard colour decoder ICs, current source
• Versatile 8-bit open-drain Input/Output (I/O) expander, 5 V tolerant
• Single 12 MHz crystal oscillator
• 3.3 V supply voltage.
SAA5264
features
• Automatic detection of transmitted pages to be selected by page up and page down
• 8 Page fastext decoder
• Table Of Pages (TOP) decoder with Basic Top Table (BTT) and Additional Information Tables (AITs)
• 4 Page user-defined list mode.
• Automatic detection of transmitted pages to be selected by page up and page down
• 8 Page fastext decoder
• Table Of Pages (TOP) decoder with Basic Top Table (BTT) and Additional Information Tables (AITs)
• 4 Page user-defined list mode.
The
SAA5264 is a single-chip ten page 625-line World System Teletext decoder with a
high-level command interface, and is SAFARI compatible.
The device is designed to minimize the overall system cost, due to the high-level command interface offering the benefit of a low software overhead in the TV microcontroller.
The SAA5264 has the following functionality:
• 10 page teletext decoder with OSD, Fastext, TOP, default and list acquisition modes
• Automatic channel installation support
• Closed caption acquisition and display
• Violence Chip (VChip) support.
The device is designed to minimize the overall system cost, due to the high-level command interface offering the benefit of a low software overhead in the TV microcontroller.
The SAA5264 has the following functionality:
• 10 page teletext decoder with OSD, Fastext, TOP, default and list acquisition modes
• Automatic channel installation support
• Closed caption acquisition and display
• Violence Chip (VChip) support.
The LM117/LM217/LM317
are monolithic integrated circuit in TO-220, ISOWATT220, TO-3 and D 2 PAK
packages intended for use as positive adjustable voltage regulators.
They are designed to supply more than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V range.
The nominal output voltage is selected by means of only a resistive divider, making the device exceptionally easy to use and eliminating the stocking of many fixed regulators.
They are designed to supply more than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V range.
The nominal output voltage is selected by means of only a resistive divider, making the device exceptionally easy to use and eliminating the stocking of many fixed regulators.
The
ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM),
organized by 8 bits.
This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
TLC7733
The
TLC77xx family of micropower supply voltage supervisors are designed for reset
control, primarily in microcomputer and microprocessor systems.
During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (. 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor:
td = 2.1 x 10 4 x CT
where
CT is in farads
td is in seconds
The TLC77xx has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, td, has expired.
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.)
The TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C, and the TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C.
During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (. 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor:
td = 2.1 x 10 4 x CT
where
CT is in farads
td is in seconds
The TLC77xx has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, td, has expired.
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.)
The TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C, and the TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C.
The 74LVC257A
is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior
to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1l 0 to 4l 0 ) are selected when input S is LOW and the data inputs from source 1 (1l 1 to 4l 1 ) are selected when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74LVC257A is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1l 0 to 4l 0 ) are selected when input S is LOW and the data inputs from source 1 (1l 1 to 4l 1 ) are selected when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs. The 74LVC257A is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance OFF-state when OE is HIGH.
The 74LVC14A is a high-performance, low power,
low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible
TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment.
The 74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment.
The 74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The LM1117
is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA
of load current. It has the same pin-out as National Semiconductor’s industry
standard LM317. The LM1117 is available in an adjustable version, which can set
the output voltage from 1.25V to 13.8V with only two external resistors. In
addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V,
and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability.
•
Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation.
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation.
IRF7314- IRF7316
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.
The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications.
The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and multiple-die capability making it ideal in a variety of power applications. With these improvements, multiple devices can be used in an application with dramatically reduced board space. The package is designed for vapor phase, infra red, or wave soldering techniques
Step-Up/Down/Inverting Switching Regulators
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC-to-DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in Step-Down and Step-Up and Voltage-Inverting applications with a minimum number of external components. Refer to Application.
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC-to-DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This series was specifically designed to be incorporated in Step-Down and Step-Up and Voltage-Inverting applications with a minimum number of external components. Refer to Application.
LM2576- 52kHz Simple 3A Buck Regulator
The
LM2576 series of monolithic integrated circuits provide all the active
functions for a step-down (buck) switching regulator. Fixed versions are
available with a 3.3V, 5V, or 12V fixed output. Adjustable versions have an
output voltage range from 1.23V to 37V. Both versions are capable of driving a
3A load with excellent line and load regulation. These regulators are simple to
use because they require a minimum number of external components and include
internal frequency compensation and a fixed-frequency oscillator. The LM2576
series offers a high efficiency replacement for popular three-terminal
adjustable linear regulators. It substantially reduces the size of the heat
sink, and in many cases no heat sink is required. A standard series of
inductors available from several different manufacturers are ideal for use with
the LM2576 series. This feature greatly simplifies the design of switch-mode
power supplies. The feedback voltage is guaranteed to ±2% tolerance for adjustable
versions, and the output voltage is guaranteed to ±3% for fixed versions,
within specified input voltages and output load conditions. The oscillator
frequency is guaranteed to ±10%. External shutdown is included, featuring less
than 200⎧A
standby current. The output switch includes cyclebycycle current limiting and
thermal shutdown for full protection under fault conditions.
Features
• 3.3V, 5V, 12V, and adjustable output versions
• Voltage over specified line and load conditions:
Fixed version: ±3% max. output voltage
Adjustable version: ±2% max. feedback voltage
• Guaranteed 3A output current
• Wide input voltage range:
4V to 40V.
Features
• 3.3V, 5V, 12V, and adjustable output versions
• Voltage over specified line and load conditions:
Fixed version: ±3% max. output voltage
Adjustable version: ±2% max. feedback voltage
• Guaranteed 3A output current
• Wide input voltage range:
4V to 40V.
•
Wide output voltage range
1.23V to 37V
• Requires only 4 external components
• 52kHz fixed frequency internal oscillator
• Low power standby mode IQ typically < 200⎧A
• 80% efficiency (adjustable version typically > 80%)
• Uses readily available standard inductors
• Thermal shutdown and current limit protection
• 100% electrical thermal limit burn-in.
1.23V to 37V
• Requires only 4 external components
• 52kHz fixed frequency internal oscillator
• Low power standby mode IQ typically < 200⎧A
• 80% efficiency (adjustable version typically > 80%)
• Uses readily available standard inductors
• Thermal shutdown and current limit protection
• 100% electrical thermal limit burn-in.
The DS90C385
transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
Features
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost.
Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
Features
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost.
•
Up to 2.38 Gbps throughput
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package.
• Up to 297.5 Megabytes/sec bandwidth
• 345 mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package.
MSP34X1G-MSP3411G Multistandard Sound Processor Family
The
MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound
processing of all analog TV-Standards worldwide, as well as the NICAM digital
sound standards. The full TV sound processing, starting with analog sound IF
signal-in, down to processed analog AF-out, is performed on a single chip.
Figure shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1) Laboratories for with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the “PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automat-ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is necessary (Automatic Sound Selection).
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1) Laboratories for with the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the “PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automat-ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is necessary (Automatic Sound Selection).
Source
Select
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling
cycle (32 kHz) are transmitted.
2. I2S _DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S _CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S _WS: The I2S _WS word strobe line defines the left and right sample.
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling
cycle (32 kHz) are transmitted.
2. I2S _DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S _CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S _WS: The I2S _WS word strobe line defines the left and right sample.
•
3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generator
• PANORAMA virtualizer algorithm
• Standard Selection with single I2C transmission
• Automatic Sound Selection (mono/stereo/bilingual),
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
• Spatial effect for loudspeaker channel, processing of all deemphasis filtering
• Two selectable sound IF (SIF) inputs
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Automatic Standard Detection of terrestrial TV standards
• Demodulation of the BTSC multiplex signal and the SAP channel
• Alignment free digital DBX noise reduction
• BTSC stereo separation (MSP 3441G also EIA-J) significantly better than specification
• SAP and stereo detection for BTSC system
• Demodulation of the FM-Radio multiplex signal.
• PANORAMA virtualizer algorithm
• Standard Selection with single I2C transmission
• Automatic Sound Selection (mono/stereo/bilingual),
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
• Spatial effect for loudspeaker channel, processing of all deemphasis filtering
• Two selectable sound IF (SIF) inputs
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Automatic Standard Detection of terrestrial TV standards
• Demodulation of the BTSC multiplex signal and the SAP channel
• Alignment free digital DBX noise reduction
• BTSC stereo separation (MSP 3441G also EIA-J) significantly better than specification
• SAP and stereo detection for BTSC system
• Demodulation of the FM-Radio multiplex signal.
TPA3002D
The
TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving
bridged-tied stereo speakers. The TPA3002D2 can drive stereo speakers as low as
8 &. The high efficiency of the TPA3002D2 eliminates the need for external
heatsinks when playing music.
FEATURES
- 9-W/Ch Into an 8-Ω Load From 12-V Supply
- Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
- 32-Step DC Volume Control From –40 dB to 36 dB
- Line Outputs For External Headphone
- Amplifier With Volume Control
- Regulated 5-V Supply Output for Powering TPA6110A2
- Space-Saving, Thermally-Enhanced PowerPAD Packaging
- Thermal and Short-Circuit Protection.
FEATURES
- 9-W/Ch Into an 8-Ω Load From 12-V Supply
- Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
- 32-Step DC Volume Control From –40 dB to 36 dB
- Line Outputs For External Headphone
- Amplifier With Volume Control
- Regulated 5-V Supply Output for Powering TPA6110A2
- Space-Saving, Thermally-Enhanced PowerPAD Packaging
- Thermal and Short-Circuit Protection.
TDA1308
The
TDA1308 is an integrated class AB stereo headphone driver contained in an SO8
or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and
has been primarily developed for portable digital audio applications. It gets
its input from two analog audio outputs (DACA_L and DACA_R) of MSP 34x0G. The
gain of the output is adjustable by the feedback resistor between the inputs
and outputs.
PI5V330
The
PI5V330 is well suited for video applications when switching composite or RGB
analog. A picturein-picture application will be described in this brief. The
pixel-rate creates video overlays so two or more
pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by
superimposing the output of a character generator on a standard composite video background.
pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by
superimposing the output of a character generator on a standard composite video background.
AD9883A
The
AD9883A is a complete 8-bit, 140 MSPS, monolithic analog interface optimized
for capturing RGB graphics signals from personal computers and workstations.
Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP surface-mount plastic package and is specified over the –40.˚C to +85. ˚C temperature range.
Features
• Industrial Temperature Range Operation
• 140 MSPS Maximum Conversion Rate
• 300 MHz Analog Bandwidth
• 0.5 V to 1.0 V Analog Input Range
• 500 ps p-p PLL Clock Jitter at 110 MSPS
• 3.3 V Power Supply.
The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A’s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP surface-mount plastic package and is specified over the –40.˚C to +85. ˚C temperature range.
Features
• Industrial Temperature Range Operation
• 140 MSPS Maximum Conversion Rate
• 300 MHz Analog Bandwidth
• 0.5 V to 1.0 V Analog Input Range
• 500 ps p-p PLL Clock Jitter at 110 MSPS
• 3.3 V Power Supply.
•
Full Sync Processing
• Sync Detect for Hot Plugging
• Midscale Clamping
• Power-Down Mode
• Low Power: 500 mW Typical
• 4:2:2 Output Format Mode
• APPLICATIONS
• RGB Graphics Processing
• LCD Monitors and Projectors
• Plasma Display Panels
• Scan Converters
• Microdisplays
• Digital TV
• Sync Detect for Hot Plugging
• Midscale Clamping
• Power-Down Mode
• Low Power: 500 mW Typical
• 4:2:2 Output Format Mode
• APPLICATIONS
• RGB Graphics Processing
• LCD Monitors and Projectors
• Plasma Display Panels
• Scan Converters
• Microdisplays
• Digital TV
SAA7118E
The
SAA7118E is a video capture device for applications at the image port of VGA
controllers. Philips X-VIP is a new multistandard comb filter video decoder
chip with additional component processing, providing high quality, optionally
scaled, video.
The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit.
It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118E accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB -PR or RGB. An expansion port (X-port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec.
At the so called image port (I-port) the SAA7118E supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.
The target application for the SAA7118E is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing.
The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit.
It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118E accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-PB -PR or RGB. An expansion port (X-port) for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec.
At the so called image port (I-port) the SAA7118E supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.
The target application for the SAA7118E is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for capture to system memory, or just to provide digital baseband video to any picture improvement processing.
Features
Video acquisition/clock
• Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert
e.g. Vestigial Side Band (VSB) signals)
• Up to eight analog Y + C inputs, split as desired
• Up to four analog component inputs, with embedded or separate sync, split as desired
• Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs)
• Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals
• Switchable white peak control
• Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
• Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties
• On-chip line-locked clock generation in accordance with “ITU 601”
• Requires only one crystal (32.11 or 24.576 MHz) for all standards
• Horizontal and vertical sync detection.
Video decoder
• Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
• Automatic detection of any supported colour standard
• Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL
M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals
– Increased luminance and chrominance bandwidth for all PAL and NTSC standards
– Reduced cross colour and cross luminance artefacts
• PAL delay line for correcting PAL phase errors
• Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals
• User programmable sharpness control
• Detection of copy-protected signals according to the macrovision standard, indicating level of protection
• Independent gain and offset adjustment for raw data path.
Component video processing.
Video acquisition/clock
• Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert
e.g. Vestigial Side Band (VSB) signals)
• Up to eight analog Y + C inputs, split as desired
• Up to four analog component inputs, with embedded or separate sync, split as desired
• Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs)
• Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals
• Switchable white peak control
• Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
• Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties
• On-chip line-locked clock generation in accordance with “ITU 601”
• Requires only one crystal (32.11 or 24.576 MHz) for all standards
• Horizontal and vertical sync detection.
Video decoder
• Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
• Automatic detection of any supported colour standard
• Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL
M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals
– Increased luminance and chrominance bandwidth for all PAL and NTSC standards
– Reduced cross colour and cross luminance artefacts
• PAL delay line for correcting PAL phase errors
• Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals
• User programmable sharpness control
• Detection of copy-protected signals according to the macrovision standard, indicating level of protection
• Independent gain and offset adjustment for raw data path.
Component video processing.
•
RGB component inputs
• Y-PB -PR component inputs
• Fast blanking between CVBS and synchronous component inputs
• Digital RGB to Y-CB -CR matrix.
Video scaler
• Horizontal and vertical downscaling and upscaling to randomly sized windows
• Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted by the transfer data rates)
• Anti-alias and accumulating filter for horizontal scaling
• Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)
• Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames
• Fieldwise switching between decoder part and expansion port (X-port) input
• Brightness, contrast and saturation controls for scaled outputs.
Vertical Blanking Interval (VBI) data decoder and slicer
• Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS) etc.
Audio clock generation
• Generation of a field-locked audio master clock to support a constant number of audio clocks per video field
• Generation of an audio serial and left/right (channel)
Digital I/O interfaces
• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)
• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-CB -CR
– Output from decoder part, real-time and unscaled
– Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals
• Discontinuous data streams supported
• 32-word x 4-byte FIFO register for video output data
• 28-word x 4-byte FIFO register for decoded VBI-data output
• Scaled 4 :2 :2, 4 :1 :1, 4 :2 :0, 4 :1 :0 Y-CB -CR output
• Scaled 8-bit luminance only and raw CVBS data output
• Sliced, decoded VBI-data output.
Miscellaneous
• Power-on control
• 5 V tolerant digital inputs and I/O ports
• Software controlled power saving standby modes supported
• Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbits/s
• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”
• BGA156 package.
• Y-PB -PR component inputs
• Fast blanking between CVBS and synchronous component inputs
• Digital RGB to Y-CB -CR matrix.
Video scaler
• Horizontal and vertical downscaling and upscaling to randomly sized windows
• Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted by the transfer data rates)
• Anti-alias and accumulating filter for horizontal scaling
• Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)
• Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames
• Fieldwise switching between decoder part and expansion port (X-port) input
• Brightness, contrast and saturation controls for scaled outputs.
Vertical Blanking Interval (VBI) data decoder and slicer
• Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS) etc.
Audio clock generation
• Generation of a field-locked audio master clock to support a constant number of audio clocks per video field
• Generation of an audio serial and left/right (channel)
Digital I/O interfaces
• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)
• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-CB -CR
– Output from decoder part, real-time and unscaled
– Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
• Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals
• Discontinuous data streams supported
• 32-word x 4-byte FIFO register for video output data
• 28-word x 4-byte FIFO register for decoded VBI-data output
• Scaled 4 :2 :2, 4 :1 :1, 4 :2 :0, 4 :1 :0 Y-CB -CR output
• Scaled 8-bit luminance only and raw CVBS data output
• Sliced, decoded VBI-data output.
Miscellaneous
• Power-on control
• 5 V tolerant digital inputs and I/O ports
• Software controlled power saving standby modes supported
• Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbits/s
• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”
• BGA156 package.
The TPS725xx
family of 1-A low-dropout (LDO) linear regulators has fixed voltage options
available that are commonly used to power the latest DSPs, FPGAs, and
microcontrollers. An adjustable option ranging from 1.22 V to 5.5 V is also
available. The integrated supervisory circuitry provides an active low RESET
signal when the output falls out of regulation. The no capacitor/any capacitor
feature allows the customer to tailor output transient performance as needed.
Therefore, compared to other regulators capable of providing the same output
current, this family of regulators can provide a stand alone power supply
solution or a post regulator for a switch mode power supply.
These regulators are ideal for higher current applications. The family operates over a wide range of input voltages (1.8 V to 6 V) and has very low dropout (170 mV at 1-A).
Ground current is typically 210 µA at full load and drops to less than 80 µA at no load. Standby current is less than 1 µA.
Each regulator option is available in either a SOT223–5, D (TPS72501 only), or DDPAK package. With a low input voltage and properly heatsinked package, the regulator dissipates more power and achieves higher efficiencies than similar regulators requiring 2.5 V or more minimum input voltage and higher quiescent currents. These features make it a viable power supply solution for portable, battery powered equipment.
Although an output capacitor is not required for stability, transient response and output noise are improved with a 10-µF output capacitor.
These regulators are ideal for higher current applications. The family operates over a wide range of input voltages (1.8 V to 6 V) and has very low dropout (170 mV at 1-A).
Ground current is typically 210 µA at full load and drops to less than 80 µA at no load. Standby current is less than 1 µA.
Each regulator option is available in either a SOT223–5, D (TPS72501 only), or DDPAK package. With a low input voltage and properly heatsinked package, the regulator dissipates more power and achieves higher efficiencies than similar regulators requiring 2.5 V or more minimum input voltage and higher quiescent currents. These features make it a viable power supply solution for portable, battery powered equipment.
Although an output capacitor is not required for stability, transient response and output noise are improved with a 10-µF output capacitor.
Unlike
some regulators that have a minimum current requirement, the TPS725 family is
stable with no output load current. The low noise capability of this family,
coupled with its high current operation and ease of power dissipation, make it
ideal for telecom boards, modem banks, and other noise sensitive applications.
Features
• 1-A Output Current
• Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V Fixed-Output and Adjustable Versions (1.2-V to 5.5-V)
• Input Voltage Down to 1.8 V
• Low 170-mV Dropout Voltage at 1 A (TPS72525)
• Stable With Any Type/Value Output Capacitor
• Integrated Supervisor (SVS) With 50-ms RESET Delay Time
• Low 210-µA Ground Current at Full Load (TPS72525)
• Less than 1-µA Standby Current
• ±2% Output Voltage Tolerance Over Line, Load, and Temperature (–40C to 125C)
• Integrated UVLO
• Thermal and Overcurrent Protection
• 5-Lead SOT223–5 or DDPAK and 8–Pin SOP (TPS72501 only) Surface Mount Package.
• 1-A Output Current
• Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V Fixed-Output and Adjustable Versions (1.2-V to 5.5-V)
• Input Voltage Down to 1.8 V
• Low 170-mV Dropout Voltage at 1 A (TPS72525)
• Stable With Any Type/Value Output Capacitor
• Integrated Supervisor (SVS) With 50-ms RESET Delay Time
• Low 210-µA Ground Current at Full Load (TPS72525)
• Less than 1-µA Standby Current
• ±2% Output Voltage Tolerance Over Line, Load, and Temperature (–40C to 125C)
• Integrated UVLO
• Thermal and Overcurrent Protection
• 5-Lead SOT223–5 or DDPAK and 8–Pin SOP (TPS72501 only) Surface Mount Package.
PCF8591
The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface.
Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I2C-bus.
The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I2C-bus.
The PCF8591 is a single-chip, single-supply low power 8-bit CMOS data acquisition device with four analog inputs, one analog output and a serial I2C-bus interface.
Three address pins A0, A1 and A2 are used for programming the hardware address, allowing the use of up to eight devices connected to the I2C-bus without additional hardware. Address, control and data to and from the device are transferred serially via the two-line bidirectional I2C-bus.
The functions of the device include analog input multiplexing, on-chip track and hold function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The maximum conversion rate is given by the maximum speed of the I2C-bus.
Features
• Single power supply
• Operating supply voltage 2.5 V to 6 V
• Low standby current
• Serial input/output via I 2 C-bus
• Address by 3 hardware address pins
• Sampling rate given by I 2 C-bus speed
• 4 analog inputs programmable as single-ended or differential inputs
• Auto-incremented channel selection
• Analog voltage range from VSS to VDD
• On-chip track and hold circuit.
• Single power supply
• Operating supply voltage 2.5 V to 6 V
• Low standby current
• Serial input/output via I 2 C-bus
• Address by 3 hardware address pins
• Sampling rate given by I 2 C-bus speed
• 4 analog inputs programmable as single-ended or differential inputs
• Auto-incremented channel selection
• Analog voltage range from VSS to VDD
• On-chip track and hold circuit.
•
8-bit successive approximation A/D conversion
• Multiplying DAC with one analog output.
• Multiplying DAC with one analog output.
PW1231
The
PW1231 is a high-quality, digital video signal processor that incorporates
Pixelworks’ patented deinterlacing, scaling, and video enhancement algorithms.
The PW1231 accepts industry-standard video formats and resolutions, and
converts the input into any desired output format.The video algorithms are
highly efficient, providing excellent quality video.
The PW1231 Video SignalProcessor combines many functions into a single device, including memory controller, auto-configuration, and others. This high level of integration enables simple, flexible, costeffective solutions featuring fewer required components.
The PW1231 Video SignalProcessor combines many functions into a single device, including memory controller, auto-configuration, and others. This high level of integration enables simple, flexible, costeffective solutions featuring fewer required components.
PW181
The
PW181 ImageProcessor is a highly integrated “system-on-a-chip” that interfaces
computer graphics and video inputs in virtually any format to a fixed-frequency
flat panel display.
Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed-frequency target display device with any resolution up to WUXGA. Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect ratio HDTV or SDTV is supported. Multi-region, nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display.
Advanced scaling techniques are supported, such as format conversion using multiple programmable regions. Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows, without user intervention.
Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on-chip. A separate memory is dedicated to storage of onscreen display images and CPU general purpose use. Advanced video processing techniques are supported using the internal frame buffer, including motion adaptive, temporal deinterlacing with film mode detection. When used in combination with the new third-generation scaler, this advanced video processing technology delivers the highest quality video for advanced displays.
Both input ports support integrated DVI 1.0 content protection using standard DVI receivers.
A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications, such as on-screen programming guides. When coupled with the new, faster, integrated microprocessor, this OSD Generator supports advanced OSD animation techniques.
Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.
Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixed-frequency target display device with any resolution up to WUXGA. Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect ratio HDTV or SDTV is supported. Multi-region, nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display.
Advanced scaling techniques are supported, such as format conversion using multiple programmable regions. Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows, without user intervention.
Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on-chip. A separate memory is dedicated to storage of onscreen display images and CPU general purpose use. Advanced video processing techniques are supported using the internal frame buffer, including motion adaptive, temporal deinterlacing with film mode detection. When used in combination with the new third-generation scaler, this advanced video processing technology delivers the highest quality video for advanced displays.
Both input ports support integrated DVI 1.0 content protection using standard DVI receivers.
A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications, such as on-screen programming guides. When coupled with the new, faster, integrated microprocessor, this OSD Generator supports advanced OSD animation techniques.
Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.
SIL151B
The
SiI 151B receiver uses PanelLink Digital technology to support high-resolution
displays up to SXGA (25-112MHz). This receiver supports up to true color panels
(24 bit/pixel, 16M colors) with both one and two pixels per clock.
All PanelLink products are designed on a scaleable CMOS architecture, ensuring support for future performance enhancements while maintaining the same logical interface. System designers can be assured that the interface will be stable through a number of technology and performance generations.
PanelLink Digital technology simplifies PC and display interface design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost.
All PanelLink products are designed on a scaleable CMOS architecture, ensuring support for future performance enhancements while maintaining the same logical interface. System designers can be assured that the interface will be stable through a number of technology and performance generations.
PanelLink Digital technology simplifies PC and display interface design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost.
Features
• Low Power Operation: 201mA max. current consumption at 3.3V core operation
• Time staggered data output for reduced ground bounce and lower EMI
• Sync Detect feature for Plug & Display iMHot Plugginglo
• Cable Distance Support: over 5m with twisted-pair, fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards compatible with VESA ® P&D TM and DFP)
• HSYNC de-jitter circuitry enables stable operation even when HSYNC contains jitter
• Low power standby mode
• Automatic entry into standby mode with clock detect circuitry
• Standard and Pb-free packages.
• Low Power Operation: 201mA max. current consumption at 3.3V core operation
• Time staggered data output for reduced ground bounce and lower EMI
• Sync Detect feature for Plug & Display iMHot Plugginglo
• Cable Distance Support: over 5m with twisted-pair, fiber-optics ready
• Compliant with DVI 1.0 (DVI is backwards compatible with VESA ® P&D TM and DFP)
• HSYNC de-jitter circuitry enables stable operation even when HSYNC contains jitter
• Low power standby mode
• Automatic entry into standby mode with clock detect circuitry
• Standard and Pb-free packages.
SDRAM 4M x 16 (MT48LC4M16A2TG-75)
The
Micron ® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM
with a synchronous interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the x4’s 16,777,216-bit banks is orga-nized
as 4,096 rows by 1,024 columns by 4 bits. Each of the x8’s 16,777,216-bit banks
is organized as 4,096 rows by 512 columns by 8 bits. Each of the x16’s
16,777,216- bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
Features
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply.
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply.
FLASH 16Mbit
The
M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low
voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or EPROM. The memory is divided
into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased. Each block can be protected independently
to prevent accidental Program or Erase commands from modifying the memory.
Program and Erase commands are written to the Command Interface of the memory.
An on-chip Program/Erase Controller
simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, The 16 KByte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals
control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered TSOP48 (12 x 20mm) and TFBGA48 (0.8mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’).
FEATURES
SUMMARYsimplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, The 16 KByte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals
control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered TSOP48 (12 x 20mm) and TFBGA48 (0.8mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’).
SUPPLY VOLTAGE
– VCC = 2.7V to 3.6V for Program, Erase and Read
ACCESS TIMES: 70, 90ns
PROGRAMMING TIME
– 10µs per Byte/Word typical
35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 32 Main Blocks
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithms
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION MODE
COMMON FLASH INTERFACE
– 64 bit Security Code
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W160ET: 22C4h
– Bottom Device Code M29W160EB: 2249h.