SAMSUNG BN44-00330B Power supply board schematic diagram - Back light inverter circuit diagram - STR-W6053 - UCC28061 - LCD television repair and service
Category: LCD Television Repair and Service
Contents of this article
- Power supply schematic diagram
- Back light inverter schematic diagram
- ICS Used
SAMSUNG BN44-00330B
STR-W6053S PWM
Regulator
The STR-W605xS series are power ICs for switching power supplies, incorporating a power MOSFET and a current mode PWM controller IC. Including a startup circuit and a standby function in the controller, the product achieves low power consumption, low standby power, and high cost-effectiveness power supply systems with few external components. The STR-W605xS internal MOSFET has a VDSSof 650 V (min), and an R DS(on) of 1.9 ohm (max) to 3.95 ohm (max) with a frequency of 67 kHz. Power output is rated at 45 to 90 W at 230 VAC input and 30 to 60 W at wide input range (85 to 265 VAC). The device is provided in an industry-standard TO-220 package, with heatsink mounting flange and pin 2 removed for increased supply isolation.
The STR-W605xS series are power ICs for switching power supplies, incorporating a power MOSFET and a current mode PWM controller IC. Including a startup circuit and a standby function in the controller, the product achieves low power consumption, low standby power, and high cost-effectiveness power supply systems with few external components. The STR-W605xS internal MOSFET has a VDSSof 650 V (min), and an R DS(on) of 1.9 ohm (max) to 3.95 ohm (max) with a frequency of 67 kHz. Power output is rated at 45 to 90 W at 230 VAC input and 30 to 60 W at wide input range (85 to 265 VAC). The device is provided in an industry-standard TO-220 package, with heatsink mounting flange and pin 2 removed for increased supply isolation.
Applications:
For switching power supplies used in:
# White goods
# Consumer electronics
# Office automation
# Industrial equipment
# Communication equipment
For switching power supplies used in:
# White goods
# Consumer electronics
# Office automation
# Industrial equipment
# Communication equipment
PIN CONFIGURATION
1 D/ST MOSFET - drain, and input for
startup current
2 – (Pin removed)
3 S/OCP MOSFET - source, and input for Overcurrent Protection detection signal
4 VCC - Input for power supply for control circuit
5 GND - Ground
6 FB/OLP - Input for constant voltage control signal, and input for Overload Protection signal
7 BR - Input for Brown-In and Brown-Out Protection detection voltage.
2 – (Pin removed)
3 S/OCP MOSFET - source, and input for Overcurrent Protection detection signal
4 VCC - Input for power supply for control circuit
5 GND - Ground
6 FB/OLP - Input for constant voltage control signal, and input for Overload Protection signal
7 BR - Input for Brown-In and Brown-Out Protection detection voltage.
UCC28061 PFC Controller
PIN CONFIGURATION
AGND - 6 - Analog ground: Connect
analog signal bypass capacitors, compensation components, and analog signal
returns to this pin. Connect the analog and power grounds at a single point to
isolate high-current noise signals of the power components from interference
with the low-current analog circuits.
COMP - 5 - Error amplifier output: The error amplifier is a transconductance amplifier, so this output is a high-impedance current source. Connect voltage regulation loop compensation components from this pin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV. During soft-start events (undervoltage, brownout, disable or output over voltage), COMP is pulled low. Normal operation only resumes after the soft-start event clears and COMP has been discharged below 0.5 V, making sure that the circuit restarts with a low COMP voltage and a short on-time. Do not connect COMP to a low-impedance source that would interfere with COMP falling below 0.5 V.
CS - 10 - Current sense input: Connect the current sense resistor and the negative terminal of the diode bridge to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current increases, the voltage on CS goes more negative. This cycle-by-cycle over-current protection limits input current by turning off both gate driver (GDx) outputs when CS is more negative than the CS rising threshold (approximately –200 mV). The GD outputs remain low until CS falls to the CS falling threshold (approximately –15 mV). Current sense is blanked for approximately 100 ns following the falling edge of either GD output. This blanking filters noise that occurs when current switches from a power FET to a boost diode. In most cases, no additional current sense filtering is required. If filtering is required, the filter series resistance must be under 100Ω to maintain accuracy. To prevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensing resistor to the CS pin through a low value external resistor. GDA 14 O Channel A and channel B gate drive output: Connect these pins to the gate of the power FET for each phase through the shortest connection practical. If it is necessary to use a trace longer than 0.5 GDB 11 O inch (12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be reduced by adding a 5-Ω to 10-Ω resistor in series with GDA and GDB.
HVSEN - 8 -High voltage output sense: The UCC28061 incorporates FailSafe OVP so that any single failure does not allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN and shuts down the PWM if either pin exceeds the appropriate over-voltage threshold. Using two pins to monitor for over-voltage provides redundant protection and fault tolerance. HVSEN can also be used to enable a downstream power converter when the voltage on HVSEN is within the operating region. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28061 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise and prevent false over-voltage shutdown.
PGND - 13 -Power ground for the integrated circuit: Connect this pin to AGND through a separate short trace to isolate gate driver noise from analog signals.
PHB - 4 - Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time for channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage constant during the phase management transient. The PHB pin allows the user to add external phase management circuitry if they desire. To disable phase management, connect the PHB pin to the VREF pin.
COMP - 5 - Error amplifier output: The error amplifier is a transconductance amplifier, so this output is a high-impedance current source. Connect voltage regulation loop compensation components from this pin to AGND. The on-time seen at the gate drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV. During soft-start events (undervoltage, brownout, disable or output over voltage), COMP is pulled low. Normal operation only resumes after the soft-start event clears and COMP has been discharged below 0.5 V, making sure that the circuit restarts with a low COMP voltage and a short on-time. Do not connect COMP to a low-impedance source that would interfere with COMP falling below 0.5 V.
CS - 10 - Current sense input: Connect the current sense resistor and the negative terminal of the diode bridge to this pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current increases, the voltage on CS goes more negative. This cycle-by-cycle over-current protection limits input current by turning off both gate driver (GDx) outputs when CS is more negative than the CS rising threshold (approximately –200 mV). The GD outputs remain low until CS falls to the CS falling threshold (approximately –15 mV). Current sense is blanked for approximately 100 ns following the falling edge of either GD output. This blanking filters noise that occurs when current switches from a power FET to a boost diode. In most cases, no additional current sense filtering is required. If filtering is required, the filter series resistance must be under 100Ω to maintain accuracy. To prevent excessive negative voltage on the CS pin during inrush conditions, connect the current sensing resistor to the CS pin through a low value external resistor. GDA 14 O Channel A and channel B gate drive output: Connect these pins to the gate of the power FET for each phase through the shortest connection practical. If it is necessary to use a trace longer than 0.5 GDB 11 O inch (12.6 mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be reduced by adding a 5-Ω to 10-Ω resistor in series with GDA and GDB.
HVSEN - 8 -High voltage output sense: The UCC28061 incorporates FailSafe OVP so that any single failure does not allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN and shuts down the PWM if either pin exceeds the appropriate over-voltage threshold. Using two pins to monitor for over-voltage provides redundant protection and fault tolerance. HVSEN can also be used to enable a downstream power converter when the voltage on HVSEN is within the operating region. Select the HVSEN divider ratio for the desired over-voltage and power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts the UCC28061 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND is recommended to filter noise and prevent false over-voltage shutdown.
PGND - 13 -Power ground for the integrated circuit: Connect this pin to AGND through a separate short trace to isolate gate driver noise from analog signals.
PHB - 4 - Phase B enable: This pin turns on/off channel B of the boost converter. The commanded on-time for channel A is immediately doubled when channel B is disabled, which helps to keep COMP voltage constant during the phase management transient. The PHB pin allows the user to add external phase management circuitry if they desire. To disable phase management, connect the PHB pin to the VREF pin.
PWMCNTL - 9 - WM
enable logic output: This open-drain output goes low when HVSEN is within
the HVSEN good region and the ZCDA and ZCDB inputs are switching correctly if
operating in two-phase mode (see PHB Pin). Otherwise, PWMCNTL is high
impedance.
TSET - 3 - Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus COMP voltage and the minimum period at the gate drive outputs.
VCC - 12- Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a 0.1-µF ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This supply powers all circuits in the device and must be capable of delivering 6 mA dc plus the transient power MOSFET gate charging current.
VINAC - 7 - Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified input power mains. When the voltage on VINAC remains below the brownout threshold for more than the brownout filter time, the device enters a brownout mode and both output drives are disabled. Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the desired brownout hysteresis.
VREF - 15 - Voltage reference output: Connect a 0.1-µF ceramic bypass capacitor from this pin to AGND. VREF turns off during VCC undervoltage and VSENSE disable to save supply current and increase efficiency. This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
VSENSE - 2 -Output dc voltage sense: Connect this pin to a voltage divider across the output of the power converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to ground through a separate short trace for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drain logic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduce VCC current. If VSENSE is disconnected, open-loop protection provides an internal current source to pull VSENSE low, turning off the gate drivers.
ZCDB - 1 - Zero current detection inputs: These inputs expect to see a negative edge when the inductor current in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupled ZCDA 16 I through a series resistor that limits the clamping current to less than ±3 mA. Connect these pins through a current limiting resistor to the zero crossing detection windings of the appropriate boost inductor. The inductor winding must be connected so that this voltage drops when inductor current decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off, the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for another falling ZCD edge.
TSET - 3 - Timing set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus COMP voltage and the minimum period at the gate drive outputs.
VCC - 12- Bias supply input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a 0.1-µF ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This supply powers all circuits in the device and must be capable of delivering 6 mA dc plus the transient power MOSFET gate charging current.
VINAC - 7 - Input ac voltage sense: For normal operation, connect this pin to a voltage divider across the rectified input power mains. When the voltage on VINAC remains below the brownout threshold for more than the brownout filter time, the device enters a brownout mode and both output drives are disabled. Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the desired brownout hysteresis.
VREF - 15 - Voltage reference output: Connect a 0.1-µF ceramic bypass capacitor from this pin to AGND. VREF turns off during VCC undervoltage and VSENSE disable to save supply current and increase efficiency. This 6 VDC reference can be used to bias other circuits requiring less than 2 mA of total supply current.
VSENSE - 2 -Output dc voltage sense: Connect this pin to a voltage divider across the output of the power converter. The error amplifier reference voltage is 6 V. Select the output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to ground through a separate short trace for best output regulation accuracy and noise immunity. VSENSE can be pulled low by an open-drain logic output or 6-V logic output in series with a low-leakage diode to disable the outputs and reduce VCC current. If VSENSE is disconnected, open-loop protection provides an internal current source to pull VSENSE low, turning off the gate drivers.
ZCDB - 1 - Zero current detection inputs: These inputs expect to see a negative edge when the inductor current in the respective phases go to zero. The inputs are clamped at 0 V and 3 V. Signals should be coupled ZCDA 16 I through a series resistor that limits the clamping current to less than ±3 mA. Connect these pins through a current limiting resistor to the zero crossing detection windings of the appropriate boost inductor. The inductor winding must be connected so that this voltage drops when inductor current decays to zero. When the inductor current drops to zero, the ZCD input must drop below the falling threshold, approximately 1 V, to cause the gate drive output to rise. When the power MOSFET turns off, the ZCD input must rise above the rising threshold, approximately 1.7 V, to arm the logic for another falling ZCD edge.
POWER SUPPLY AND BACK LIGHT INVERTER CIRCUIT DIAGRAM
