ALL ABOUT SOUTH BRIDGE CHIP SET VOLTAGE AND SIGNALS IN LAPTOP AND DESKTOP MOTHERBOARDS.
IT IS VERY IMPORTANT FOR LAPTOP AND DESKTOP MOTHERBOARD REPAIRING, WHAT ARE THE MAIN FUNCTIONS OF SOUTH BRIDGE IC.
1.RTC circuit: Southbridge internal real time clock circuit, also called CMOS circuits, mainly used to store the time and date and ESCD (Extended System Configuration Data) .
2. Return circuit (module): is part of the South Bridge internal power management module, all the signals are thus SLP module circuit is completed.
3.VccSus: back module (module restart) power ICH4 inside, there are three V5REF_Sus VccSus3_3 VccSus1_5 and power.
Wherein VccSus3_3 return module I / O buffer circuit power;
VccSus1_5 is mains voltage return module '
V5REF_Sus return module 5V reference voltage input.
4.PWROK: This signal is sent to the ICH4M representative ICH4 core voltage of the normal power-good signal from the outside, when PWROK canceled, ICH4 will refer PCIRST #.
It is worth noting that in three of the RTC clock, PWROK failure. So as to ensure ICH4 produce normal PCIRST #.
5.VGATE / VRMPWRGD (VGATE / VRM Power Good): This is generated by the CPU core power manager output power to the representatives of CPU ICH4 normal power-good signal.
6.CPUPWRGD (CPU Power Good): This is ICH4 output to the CPU power of a good signal, is connected to the CPU. Southbridge asserts this signal is intended to tell all the CPU power is normal, you can put on standby. This signal is internally ICH4 after PWROK and VGATE / VRMPWRGD phase formation.
7.RSMRST #: Southbridge desired return module reset signal input.
8.SUS_STAT # (suspend statas): Pending status indication. When this signal is referenced, the system will enter a low power state.
9.V_CPU_IO #: CPU's I / O power supply, Southbridge need this power to the output interface signal processor.
10.SUSCLK: South Bridge RTC circuit generates hang clock used to refresh external clock chip as used. Often used in the IBM, SONY and other machines. In standby, when the clock to the motherboard EC / KBC (usually H8S) later, EC / KBC will enter a low-power mode, then jump into the H8S own shock wave state.
11.SYS_RESET # (system reset): This signal is input to Southbridge Southbridge and dried after debouncing will be forced to reset the internal logic of Southbridge, enabling the machine to reboot
1.RTC circuit: Southbridge internal real time clock circuit, also called CMOS circuits, mainly used to store the time and date and ESCD (Extended System Configuration Data) .
2. Return circuit (module): is part of the South Bridge internal power management module, all the signals are thus SLP module circuit is completed.
3.VccSus: back module (module restart) power ICH4 inside, there are three V5REF_Sus VccSus3_3 VccSus1_5 and power.
Wherein VccSus3_3 return module I / O buffer circuit power;
VccSus1_5 is mains voltage return module '
V5REF_Sus return module 5V reference voltage input.
4.PWROK: This signal is sent to the ICH4M representative ICH4 core voltage of the normal power-good signal from the outside, when PWROK canceled, ICH4 will refer PCIRST #.
It is worth noting that in three of the RTC clock, PWROK failure. So as to ensure ICH4 produce normal PCIRST #.
5.VGATE / VRMPWRGD (VGATE / VRM Power Good): This is generated by the CPU core power manager output power to the representatives of CPU ICH4 normal power-good signal.
6.CPUPWRGD (CPU Power Good): This is ICH4 output to the CPU power of a good signal, is connected to the CPU. Southbridge asserts this signal is intended to tell all the CPU power is normal, you can put on standby. This signal is internally ICH4 after PWROK and VGATE / VRMPWRGD phase formation.
7.RSMRST #: Southbridge desired return module reset signal input.
8.SUS_STAT # (suspend statas): Pending status indication. When this signal is referenced, the system will enter a low power state.
9.V_CPU_IO #: CPU's I / O power supply, Southbridge need this power to the output interface signal processor.
10.SUSCLK: South Bridge RTC circuit generates hang clock used to refresh external clock chip as used. Often used in the IBM, SONY and other machines. In standby, when the clock to the motherboard EC / KBC (usually H8S) later, EC / KBC will enter a low-power mode, then jump into the H8S own shock wave state.
11.SYS_RESET # (system reset): This signal is input to Southbridge Southbridge and dried after debouncing will be forced to reset the internal logic of Southbridge, enabling the machine to reboot
